KEMI Docs · PCB Practice

How to Choose PCB Trace Width for Current

Last updated: 2026-10-04

Type a current into a trace width calculator and it gives you one number. What it does not tell you is which assumptions that number rests on (copper weight, external or internal layer, allowed temperature rise), or whether the trace also meets your voltage-drop budget. This article covers the two criteria that set trace width (temperature rise and voltage drop), the difference between IPC-2221 and its successor IPC-2152, and how to handle vias and high-current copper, in the order we use during layout reviews.

A trace is a resistor. Current through it generates I²R heat and raises its temperature (the thermal criterion), and it drops I × R volts (the voltage-drop criterion). Short traces are usually limited by heating; long traces and low-voltage, high-current rails are usually limited by voltage drop. Most calculators only do the thermal part, so check voltage drop separately.

Copper thickness is specified by weight: one ounce of copper spread over one square foot. 1 oz is about 1.37 mil (35 µm), 0.5 oz about 0.7 mil (17.5 µm), 2 oz about 2.7 mil (70 µm). Two practical checks. First, outer layers get plating on top of the base foil, so fabs state it differently: '0.5 oz base plus plating' may be sold as roughly 1 oz finished. Confirm whether your fab's copper spec is base or finished. Second, budget multilayer boards often default to 0.5 oz on inner layers. If you plan to run power on an inner layer, make sure you actually ordered 1 oz inner copper.

The most widely used equation is from IPC-2221 (descended from IPC-D-275): I = k × ΔT^0.44 × A^0.725. I is current in amps, ΔT is the allowed temperature rise in °C, A is the cross-section in square mils, and k is 0.048 for external and 0.024 for internal traces. Divide the area by copper thickness to get width (1 oz = 1.378 mil). The equation gives the following.

Two things stand out. Doubling the current needs about 2.6× the width; width and current are not proportional. And under IPC-2221 an internal trace needs about 2.6× the width of an external one for the same current. That internal derating being far too conservative is one of the key findings of IPC-2152.

The IPC-2221 charts trace back to measurements made decades ago. IPC-2152, published in 2009, was built on new test data and showed three things. (1) Internal traces are not nearly as disadvantaged as IPC-2221 says; the internal/external gap is much smaller. (2) The surroundings matter more than the trace itself: nearby copper planes, board thickness, the board material's thermal conductivity and how the board is mounted all have a bigger effect on temperature rise. (3) So IPC-2152 provides baseline charts for a conservative reference case (a test board without planes, in still air) and applies modifiers for your actual conditions. In a typical multilayer board with planes nearby, that means you can reach the same temperature rise with a narrower trace.

• ΔT 10 °C (18 °F): the conservative default, for designs with headroom, sealed enclosures and hot environments.
• ΔT 20 °C (36 °F): commonly accepted in general products, and it cuts width by about a third.
• ΔT 30 °C (54 °F) and up: only after adding up the temperature limits of nearby components, the laminate's glass transition temperature (Tg, about 130 to 140 °C for standard FR-4) and the ambient temperature.
• Ambient, trace rise and component self-heating stack. A ΔT 20 °C trace running past an electrolytic capacitor inside a 40 °C enclosure puts that capacitor in a 60 °C environment.

Trace resistance is R = ρ × L / (W × T). Copper resistivity ρ is 1.72 × 10⁻⁸ Ω·m at 20 °C and rises about 0.39% per °C. A 1 oz trace 1 mm (39 mil) wide and 100 mm (3.9 in) long is about 49 mΩ.

Say a 12 V, 3 A motor-driver supply runs 60 mm (2.4 in) on an external 1 oz layer. IPC-2221 at ΔT 10 °C gives 1.37 mm (54 mil). That trace is about 21.5 mΩ over 60 mm: a 65 mV drop and 0.19 W of heat at 3 A. On a 12 V rail, 65 mV is 0.5%, no problem. If the same 3 A feeds a 3.3 V rail, though, 65 mV is 2%, and counting the return path it approaches 4%. Here you widen the trace to 2 mm (80 mil) or more or turn it into a pour, and run ground as a plane to eliminate return-path resistance. Try to route that 3 A on a 0.5 oz inner layer of a budget 4-layer board and IPC-2221's internal value exceeds 7 mm (280 mil). At that point it is not a trace anymore; treat it as an inner-layer plane region.

A via is a plated cylinder. With 25 µm (1 mil) of plating, a 0.3 mm (12 mil) drill via has about 0.026 mm² of copper, roughly the same as a 0.7 mm (28 mil) wide 1 oz trace. Because a via is short and sheds heat into the copper on both ends, its real margin is better than cross-section alone suggests. Our conservative rule is about 1 A per 0.3 mm via, placed in parallel to cover the current: at least 3 to 4 vias for a 3 A path, six for comfort. Extra vias cost almost nothing, so don't skimp. See our via article for dimensions and treatment options.

• Pours instead of traces. Above a few amps, draw areas (copper pours), not lines. The wider the copper, the lower both resistance and temperature rise.
• Parallel layers. Pour the same shape on top and bottom and stitch them densely with vias to double the cross-section.
• 2 oz copper. Heavier copper is the surest fix on high-current boards. It enlarges minimum trace and space rules, so check fab rules first if you have fine-pitch parts.
• Remove necks. A wide pour that narrows at a pad entry or between vias bottlenecks at that point. A row of vias that turns a pour into Swiss cheese cuts the effective width the same way.
• Check thermal reliefs. A high-current pad tied to a pour through a thermal relief (four thin spokes) forces all the current through those spokes. Use a solid connection or wide spokes on high-current paths, and accept that hand soldering gets harder.
• Solder mask opening plus solder. Opening the mask and adding solder increases cross-section, but solder's resistivity is about 7 to 8 times copper's, so a 0.1 mm (4 mil) solder layer equals only about 13 µm (0.5 mil) of copper. To get a real benefit you need a thick build-up or a copper bus bar or wire on top, and the uneven thickness makes it unusable as a design value.
• Return current is the same current. A thin ground path heats and drops voltage too. Use a ground plane on high-current circuits.
• Neighboring traces. Standard values are for a single trace. Several high-current traces side by side heat each other, so add margin.
• Look for the real bottleneck. A trace rated for 10 A doesn't help if the connector pin is rated for 3 A.

• Using a calculator's defaults (external, 1 oz, ΔT 10 °C) for an internal trace without noticing.
• Checking heating but not voltage drop. Common on long, low-voltage rails.
• Designing for 1 oz when the inner layers are actually 0.5 oz.
• Sizing for pulse peak current, or for average current. Calculate heating from RMS current and check voltage drop at peak current.
• Leaving thermal reliefs on high-current pads.
• Changing layers through one via. The trace handles 3 A and the single via becomes the bottleneck.

1. Have you listed the maximum (RMS) and peak current of every power path?
2. Is copper weight fixed for outer and inner layers, and do you know whether it is base or finished?
3. Did you choose ΔT to suit the product environment?
4. Did you calculate thermal width separately for external and internal layers?
5. Did you calculate voltage drop over the round trip, and is it within rail tolerance?
6. Do layer-change vias match the current (about 1 A per 0.3 mm via)?
7. Did you check pour necks, thermal reliefs and Swiss-cheese via rows?
8. Are there other bottlenecks in the path, such as connectors, fuses or component pads?

This article summarises the working rules KEMI uses in real design and fabrication work. For production, part datasheets and fab specifications take precedence.