KEMI Docs · PCB Practice
Via Types and How to Choose
Last updated: 2026-08-30
A via is a plated hole connecting layers. It looks like a free commodity, but the type you choose multiplies fab cost and the dimensions you choose decide reliability. Here is what to use when, the customary sizes, and what the 'via treatment' order option actually means.
1
Types
| Type | Connects | Cost | When |
|---|---|---|---|
| Through via | all layers | baseline | Most designs — through vias alone carry you to 4-6 layers |
| Blind via | outer ↔ adjacent inner | several times more | Outer-layer density limits (BGA fanout) |
| Buried via | inner ↔ inner | high | Dense 8+ layer boards |
| Microvia | adjacent layers, laser-drilled ~0.1mm | HDI process | 0.4mm-pitch BGAs, HDI |
| Via-in-pad | via inside a pad | extra process (fill & cap required) | QFN thermal pads, extreme fanout |
⚠ Blind and buried vias are not an upgrade
Drillable layer pairs are constrained by the stack-up and require prior agreement with the fab. If a routine 4-6 layer design 'needs' blind vias, the real fix is usually better placement.
2
Customary dimensions
| Use | Drill/pad (mm) | Notes |
|---|---|---|
| General signal | 0.3 / 0.6 | the no-surcharge standard on budget processes |
| Tight routing | 0.25 / 0.5 | surcharge boundary at some fabs |
| Power/GND | 0.4 / 0.8+, several in parallel | size for margin, then divide current across count |
| Thermal | 0.3 / 0.6 in a grid | e.g. 3×3 under a QFN pad |
| Component holes (PTH) | lead diameter + 0.2-0.3 | component holes, not vias — allow drill margin |
3
Via treatment — that order option
Tenting (mask over the via) is the free default. Plugging (resin fill) is for vias near connectors or test pads where solder must not wick in. Filled & capped (copper fill + plating) is mandatory for via-in-pad — an unfilled via in a pad drinks the solder during reflow and leaves the joint starved.
4
A note on signal quality
Every via is a small impedance discontinuity. Below a few hundred MHz, ignore it. For multi-gigabit differential pairs: minimise via count, switch layers for both lines at the same point, and place a ground via nearby so the return current can follow.
Fewer vias is craft
Unnecessary layer changes cost routing length, return-path integrity and inspection effort. KEMI's own routing rules start with 'no wasted routing, minimum vias'.
FAQ
Tent vias or leave them open?
Tent signal vias by default — less short and corrosion risk. Open only intentional test points and thermal vias.
Why are drills under 0.3mm expensive?
Thin bits break, machines slow down, and the aspect ratio (board thickness vs hole) makes plating harder. Below 0.2mm expect surcharges; below 0.15mm you are in laser/HDI territory.
How many power vias in parallel?
A comfortable working rule is roughly 1A per 0.3mm via with margin, then parallel up to the current you need — extra vias are nearly free.
Solder leaks through my QFN thermal vias.
Classic symptom of open thermal vias — solder wicks to the far side during reflow. Manage with far-side mask openings, or specify filled & capped vias to fix it properly.
See also
This article summarises the working rules KEMI uses in real design and fabrication work. For production, part datasheets and fab specifications take precedence.