KEMI Docs · PCB practice
PCB Thermal Design — Copper, Thermal Vias and θ Math
Last updated: 2026-09-16
Thermal design is subtraction and multiplication, not intuition. Multiply the power a part dissipates (W) by its thermal resistance (°C/W), and check whether the rise exceeds the allowed junction temperature. This article covers reading θ values from a datasheet, how much copper area and thermal vias actually lower them, and the fabrication options (2oz copper, aluminium substrate) with numbers.
1
Temperature rise = power × thermal resistance
θJA (junction-to-ambient) in a datasheet means 'how many °C per watt on the standard test board'. SOT-223 is about 60°C/W, DPAK about 40°C/W, a 4×4 QFN with exposed pad about 35°C/W — and because these are test-board figures, your board can land anywhere from half to double depending on copper. Example: an SOT-223 LDO burning 0.8W rises 60 × 0.8 = 48°C; in a 40°C enclosure the junction sits at 88°C. Most parts allow 125°C, but the rule of thumb that lifetime halves per 10°C is worth remembering.
2
How much copper area lowers θ
| Heat-spreading copper (1oz) | SOT-223 θJA approx. | Rise at 1W |
|---|---|---|
| Minimum pad only | ≈ 90°C/W | 90°C — no |
| 10×10 mm pour | ≈ 60°C/W | 60°C — marginal |
| 25×25 mm pour | ≈ 45°C/W | 45°C — workable |
| 25×25 mm + bottom pour + 9 vias | ≈ 35°C/W | 35°C — comfortable |
| 2oz copper + bottom + vias | ≈ 30°C/W | 30°C |
These are practical roundings of the curves manufacturers' app notes agree on. The key point is saturation: beyond about 25×25 mm, doubling the area buys less than 5°C/W. The next lever is moving heat to the other side with thermal vias.
3
Thermal vias — count, size, placement
- Size: 0.3 mm drill, 0.6 mm pad is standard. Larger drills help little because conduction is through the ~25 µm plated wall; more vias beat bigger vias.
- Count: a 1.0-1.2 mm grid under the exposed pad naturally gives 9 vias for a 4×4 QFN and 16 for a 5×5.
- Placement: directly under the heat source first, then the surrounding pour. Vias more than 5 mm from the source contribute almost nothing.
- Reflow trap: vias in the exposed pad wick solder and leave voids. Order with via tenting (mask over the bottom) or shift the vias just outside the pad.
4
What fabrication options solve
| Option | Effect | Cost feel |
|---|---|---|
| 2oz copper (70 µm) | ~30% lower copper θ, more current capacity | modest premium over 1oz |
| Aluminium substrate (MCPCB) | large θ reduction for LED/power boards (single-sided only) | 2-3× a single-sided FR-4 |
| Thicker board (2.0 mm) | almost no thermal effect — for stiffness | small premium |
| ENIG finish | unrelated to heat — flatness | premium over HASL |
KEMI's review order
1) power × θJA → pass if the rise is under 40°C. 2) Otherwise 25×25 mm copper plus bottom-side vias. 3) Still over → change the part (a buck converter removes the loss more cheaply than any heatsinking). Heatsinks and fans come last.
⚠ A common mistake
An isolated island of heat-spreading copper has nowhere to send the heat. Tie it to the GND plane, or at least stitch it to a large plane with vias.
FAQ
θJA vs θJC?
θJC is junction-to-case (usually the exposed pad) and belongs to the part; θJA adds board and air. Only the board share of θJA is yours to design.
What rise is acceptable?
Practice: junction under 100°C at 40°C ambient, i.e. a rise under 60°C as the safety line, and under 40°C for products where lifetime matters.
Are filled vias better?
Copper-filled vias conduct well but cost a lot. For ordinary products, more plain vias buy the same effect far more cheaply.
See also
This article summarises the working rules KEMI uses in real design and fabrication work. For production, part datasheets and fab specifications take precedence.