KEMI Docs
PCB Design Basics
How to pick a layer stack-up, IPC-2221-based trace width per current with voltage-drop math, and via dimensions with per-purpose selection. Three representative sheets excerpted from the KEMI PCB Design & Manufacturing Reference (printable sheets); tables and worked figures are transcribed as published.
Excerpt 1
Layer Stack-up
How to pick a layer count
| Layers | Typical assignment | Suits | Upside | Limits |
|---|---|---|---|---|
| 1 | All on Top: routing, power, GND | LED bars, simple supply / relay boards | Cheapest, shortest lead time | Needs jumpers, no GND plane, poor EMI |
| 2 | L1 signal / L2 solid GND | MCU and sensor boards, slow digital | A real reference plane at low cost | Power runs as traces, density limited |
| 4 | Sig – GND – PWR – Sig | Multi-rail, controlled impedance, fast links | Both signal layers face a plane, plus plane capacitance | Costs more than 2 layer, stack-up must be specified |
| 6 | Sig – GND – Sig – Sig – PWR – Sig | Dense BGAs, memory buses, mixed analog | Inner signals shielded between planes (stripline) | Cost and thickness control, agree stack-up with the fab |
Material thicknesses
Copper thickness t [µm] ≈ 35 × oz · finished thickness = Σ (core + prepreg + copper + solder mask)
| Item | Typical | Notes |
|---|---|---|
| Finished | 0.6 / 0.8 / 1.0 / 1.6 / 2.0 mm | 1.6 mm default |
| Core (FR-4) | 0.1 – 1.5 mm | 1.065 mm in 1.6 mm 4-layer |
| Prepreg / sheet | 0.10 – 0.19 mm | count sets dielectric |
| Copper 0.5 oz | 17.5 µm | inner default |
| Copper 1 oz | 35 µm | outer default, + plating |
| Copper 2 oz | 70 µm | high current |
| Solder mask | 10 – 25 µm per side | counts to total |
| 1.6 mm 4-layer check | 35+200+17.5+1065+17.5+200+35 = 1570 + mask 2×15 = 1600 µm = 1.60 mm | a typical 4-layer build |
Typical FR-4 values — every fab has its own house stack-up, so confirm before ordering.
Three rules for assigning layers
- ① Every signal layer needs a reference plane next to it — the return current needs a path directly under the trace.
- ② Face GND and PWR across a thin dielectric — the two planes form a capacitor on their own and pull down high-frequency supply impedance.
- ③ For 4 layers, Sig–GND–PWR–Sig is the safe choice. With Sig–GND–Sig–PWR the L3 signals reference a split PWR plane, so the return breaks wherever a trace crosses a rail boundary.
An asymmetric build warps — if copper coverage and dielectric heights differ above and below the centre line, the board bows in reflow heat and BGA joints fail. A symmetric stack-up plus balanced copper in empty areas (dummy copper) is a baseline, not an option. The classic 2-layer mistake — treating the bottom GND as spare space and routing across it, splitting the plane. Once split, the only advantage a 2-layer board had is gone.
Excerpt 2
Trace Width & Current
1 oz (35 µm), in mm · first 3 columns calculated, last practical.
| Current(A) | Outer ΔT=10 °C | Outer ΔT=20 °C | Inner ΔT=10 °C | Notes — practical width (outer) and why |
|---|---|---|---|---|
| 0.1 | 0.013 | 0.008 | 0.033 | 0.20 — below the fab minimum; use your default signal width. |
| 0.25 | 0.044 | 0.029 | 0.115 | 0.25 — the floor here is manufacturing, not heating. |
| 0.5 | 0.115 | 0.076 | 0.300 | 0.30 — practical minimum for logic and sensor feeds. |
| 1 | 0.300 | 0.197 | 0.781 | 0.50 — about 1.7× calculated, drop margin included. |
| 2 | 0.781 | 0.513 | 2.033 | 1.20 — from here voltage drop binds first. |
| 3 | 1.367 | 0.898 | 3.556 | 2.00 — use a copper pour rather than a trace. |
| 5 | 2.765 | 1.816 | 7.194 | 4.00, or 2.0 mm in 2 oz copper. |
| 10 | 7.194 | 4.724 | 18.715 | Not a trace — 2 oz or heavier plus a pour, or a bus bar. |
I = k · ΔT0.44 · A0.725 (A: cross-section in mil², outer k = 0.048 / inner k = 0.024) · width[mil] = A ÷ 1.378 (1 oz) · width[mm] = width[mil] × 0.0254
Resistance and voltage drop
1 oz, ρ = 1.72×10⁻⁸ Ω·m · table value × (length/100 mm) × current · 2 oz halves resistance
| Width(mm) | 1 oz section(mm²) | R per 100 mm(mΩ) | Drop at 1 A(mV/100 mm) |
|---|---|---|---|
| 0.2 | 0.0070 | 245.7 | 245.7 |
| 0.3 | 0.0105 | 163.8 | 163.8 |
| 0.5 | 0.0175 | 98.3 | 98.3 |
| 0.8 | 0.0280 | 61.4 | 61.4 |
| 1.0 | 0.0350 | 49.1 | 49.1 |
| 2.0 | 0.0700 | 24.6 | 24.6 |
Worked example · 2 A on a 3.3 V rail
0.5 mm trace, 80 mm long: ① A = 0.5 × 0.035 = 0.0175 mm² ② R = ρL/A = 1.72e-8 × 0.080 ÷ 1.75e-8 = 78.6 mΩ ③ Drop = 2 A × 78.6 mΩ = 157 mV → 4.8 % of 3.3 V ④ Loss in the trace = I²R = 4 × 0.0786 = 0.31 W Budget is 1–2 % of the rail (33–66 mV here). 4.8 % blows it — the load sees only 3.14 V, inviting brownouts and ADC reference error. Fix, checked: for 1 %, R ≤ 16.5 mΩ → width 0.5 × (78.6/16.5) ≈ 2.4 mm (or 1.2 mm in 2 oz)
Rules of thumb
- · 1 oz outer, ΔT 10 °C → 1 mm wide ≈ 2.4 A
- · ΔT of 20 °C buys ×1.36 current · inner layers get half (k halved)
- · Doubling current needs about 2.6× width — width and current are not proportional.
- · Never use a thin trace as a fuse — the current at which it opens is not repeatable, and it can char the laminate or take neighbours with it. Protect with a fuse, polyfuse or current-limiting IC.
Excerpt 3
Via Design
Via dimension specs
Standard = no added cost / Advanced = adds cost and lead time
| Item | Standard | Advanced | Notes |
|---|---|---|---|
| Finished hole Ø (drill) | 0.30 mm | 0.15–0.20 mm | Mechanical drill floor — below this it is laser (HDI) |
| Pad Ø (land) | 0.60 mm | 0.40 mm | Hole Ø plus one annular ring per side — see formula |
| Annular ring (per side) | 0.15 mm | 0.10 mm | Margin that absorbs drill registration error |
| Aspect ratio (AR) | 8 : 1 | 10 : 1 | Exceed it and barrel plating thins — cracks, opens |
| Via ↔ via (pad to pad) | 0.20 mm | 0.13 mm | Copper gap between pad edges |
| Via ↔ trace | 0.20 mm | 0.13 mm | Matching the fab's minimum space is safest |
Pad Ø = hole Ø + 2 × annular ring → 0.30 + 2×0.15 = 0.60 mm · AR = board thickness ÷ hole Ø → 1.6 ÷ 0.20 = 8.0 : 1 (at the limit) · 1.6 ÷ 0.30 = 5.3 : 1 (comfortable)
Choosing a via by purpose
| Purpose | Hole / pad | How many |
|---|---|---|
| General signal | 0.3 / 0.6 | One per net — better yet, avoid the layer change |
| High-speed signal | 0.2 / 0.45 | A return GND via within 2 mm |
| Power branch | 0.3 / 0.6 | One per amp, minimum two |
| High-current plane | 0.4–0.5 / 0.8–0.9 | One per amp, spread out |
| GND stitching | 0.3 / 0.6 | 5–10 mm grid (λ/20 ≈ 7 mm @ 1 GHz), plane edges first |
| Thermal | 0.3 / 0.6 | 1.0–1.2 mm grid under the pad |
Do not do this
- ① An unfilled, uncapped via in pad — solder wicks down the hole in reflow and the part lifts. Specify fill + copper cap + planarization.
- ② A via used as a test point needs a mask opening; ordinary vias are tented by default — the opposite.
- ③ Via stubs — a through via between two upper layers leaves a barrel that acts as an antenna, wrecking high-speed signals. Reassign layers or back-drill.
- ④ Microvias, blind and buried vias are not standard process — confirm the fab builds them; cost and lead time rise sharply.
Current per via — assuming 25 µm barrel plating, a 0.30 mm via has 0.026 mm² of copper, equivalent to a 0.73 mm trace in 1 oz. A copper-area comparison only; real capacity is set by heating — budget ≈ 1 A per 0.30 mm via and add vias.
This document is an excerpt
The full PDF edition of the PCB Design & Manufacturing Reference covers footprints and land patterns, component placement rules, ground and return paths, decoupling, differential pair routing, silkscreen conventions, DRC rule setup, a pre-order final checklist and a field guide of common mistakes — all as printable sheets plus practice worksheets.
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How wide should a trace be for 1 A?
The IPC-2221 calculated width at 1 oz copper, outer layer, ΔT 10 °C is 0.300 mm, but the practical recommendation is about 1.7× that — 0.50 mm — to include voltage-drop margin. Rule of thumb: 1 oz outer at ΔT 10 °C, 1 mm wide ≈ 2.4 A; doubling current needs about 2.6× the width — width and current are not proportional.
How should I assign a 4-layer stack-up?
Sig–GND–PWR–Sig is the safe choice. With Sig–GND–Sig–PWR the L3 signals reference a split PWR plane, so the return breaks wherever a trace crosses a rail boundary. Sig–GND–PWR–Sig gives both signal layers a solid plane to face, and plane capacitance for free.
How much current can a single via carry?
Assuming 25 µm barrel plating, a 0.30 mm via has 0.026 mm² of copper — equivalent to a 0.73 mm trace in 1 oz — but real capacity is set by heating. Budget conservatively at about 1 A per 0.30 mm via, and put vias in parallel on high-current paths.
This document is an excerpt of KEMI's own reference material and an unofficial study reference. Trace widths are computed from the published IPC-2221 formula; real capacity varies with plating, ambient temperature and cooling — confirm against fab specs (ΔT is a rise above ambient). IPC is a trademark of IPC; all trademarks mentioned are the property of their respective owners.