PCB Impedance Calculator

Characteristic impedance (Z0) is the ratio of voltage to current that a signal wave experiences as it travels down a trace. It is set by the trace's inductance and capacitance per unit length, Z0 = √(L/C), and — unlike resistance — it does not depend on length. Once a signal's rise time is short compared with the time it takes to travel the trace, every point where the impedance changes reflects part of the signal back, causing ringing, overshoot and false triggering. That's why interfaces specify an impedance: 90 Ω differential for USB, 100 Ω differential for Ethernet, HDMI and LVDS, 85 Ω differential for many PCIe designs, and 50 Ω single-ended for RF and most high-speed single-ended nets. Wider traces, a closer reference plane (smaller H) and a higher dielectric constant all increase C and therefore lower the impedance.

A common rule of thumb is to treat a trace as a transmission line once its one-way delay exceeds roughly one-sixth of the signal's rise time (designers quote anything from 1/4 to 1/10). Outer-layer FR-4 microstrip propagates at roughly 140–150 ps/inch and stripline at around 170–180 ps/inch, so with a 1 ns edge the critical length is only about an inch. Note that it's the edge rate that matters, not the clock frequency: a 1 MHz signal from a modern fast-edged driver can still ring on a long trace.

Microstrip:     Z0 = 87 / √(εr + 1.41) × ln( 5.98H / (0.8W + T) )
Stripline:      Z0 = 60 / √εr × ln( 1.9B / (0.8W + T) ),   B = 2H + T
Diff microstrip: Zdiff ≈ 2·Z0 × (1 − 0.48·e^(−0.96·S/H))
Diff stripline:  Zdiff ≈ 2·Z0 × (1 − 0.347·e^(−2.9·S/B))
Delay:          tpd = √εeff / c  ≈ 84.7 × √εeff  ps/inch

These are the closed-form equations from IPC-2141 (and the earlier National Semiconductor application notes they share with). Because their accuracy is limited, the calculator also computes an independent cross-check: the Hammerstad–Jensen equations for microstrip, which include a thickness correction and are accurate to around 1% over a much wider W/H range, and Wheeler's thickness-corrected stripline equation, which reduces to the exact conformal-mapping solution when T → 0. When the two values disagree by more than a few percent, you're probably near the edge of the IPC-2141 validity range.

Worked example (imperial)

A typical 4-layer, 62 mil board has about 8 mil of prepreg between the top layer and the L2 ground plane. With εr = 4.2 and 1.4 mil copper, IPC-2141 says a 50 Ω microstrip needs W ≈ 13.6 mil, while Hammerstad–Jensen gives about 14.6 mil — a 7% spread that shows why closed-form numbers are only a starting point. The effective permittivity is about 3.07, so the delay is roughly 148 ps/inch. For a 100 Ω differential pair on the same layer with S = 8 mil, IPC-2141 gives W ≈ 9.5 mil. Now try a 2-layer 62 mil board, where the reference plane is the bottom layer (H ≈ 62 mil): 50 Ω needs a trace over 110 mil wide, which won't connect to anything fine-pitch. That single fact is the main reason controlled-impedance designs move to four or more layers.

It's also worth seeing how sensitive the result is. Starting from the 14.6 mil, 50 Ω microstrip above: making the dielectric 10% thicker raises Z0 to about 52.9 Ω; raising εr from 4.2 to 4.5 lowers it to about 48.5 Ω; and etching the trace 1 mil narrower lifts it to about 52 Ω. Fabricators therefore quote impedance control as ±10% (±5% at extra cost), and adjust width and dielectric thickness themselves to hit your target.

• Solder mask: covering a microstrip with mask raises the effective permittivity and usually lowers Z0 by a few ohms.
• Etch trapezoid: real traces are narrower at the top than the bottom.
• Copper roughness and frequency-dependent loss.
• Dk dispersion: FR-4's dielectric constant drops with frequency, so a datasheet value at 1 MHz is too high for GHz signals. Use the value at your operating frequency, and remember prepreg and core can differ because of resin content.
• Nearby copper pour: ground fill close to the trace turns it into a coplanar waveguide and lowers Z0. Keep pours at least about 3× the trace width away, or model it as coplanar.

Expect the closed-form results to be within roughly ±5–10% of reality. For production, have your fabricator confirm the stack-up and calculate widths with a 2D field solver.

• Using the full board thickness for H on an outer layer: H is the distance to the nearest reference plane (L2 on a 4-layer board), not to the bottom side.
• Routing over a split plane: crossing a gap in the reference plane breaks both the impedance and the return path.
• Entering nominal copper for outer layers: plating makes the finished outer copper thicker than the base foil.
• Changing differential pair spacing near connectors or vias without accounting for the local impedance change.
• Assuming the diff-pair formula works for very loosely coupled pairs: as S grows, Zdiff simply approaches 2 × Z0.

Production impedance is set by your fabricator's actual stack-up — prepreg style, resin content and finished thickness — not by any online calculator. In your fabrication notes, state which nets on which layers need which impedance, the tolerance (typically ±10%) and the reference planes; the fab will fine-tune widths and verify with TDR test coupons. At KEMI we lay out controlled-impedance boards against the fabricator's stack-up and carry the same data straight through PCB fabrication.