KEMI Docs · PCB Practice

How to Order a Controlled Impedance PCB

Last updated: 2026-10-04

The first time you build a board with USB, Ethernet or an RF antenna feed, you run into an order option called 'impedance control'. It looks like a checkbox, but it is really an agreement between designer and fab on stack-up, trace geometry and measurement method. Skip that agreement and the fab doesn't know what to hit, and you have no way to verify that the boards you received were built right. This guide covers when you need controlled impedance, why the stack-up has to be settled before trace width, tolerance and measurement (coupons and TDR), and the notes to put on your fab drawing, in the order an actual order goes.

When you need it

A trace's characteristic impedance is the ratio of voltage to current a signal sees as it travels down the trace. When a trace is short relative to the signal's rise time, it behaves like a plain wire and impedance doesn't matter. Once it gets long, reflections make the waveform ring, and from then on the trace impedance must match the driver and receiver. The usual rule of thumb: start caring when the trace is longer than about one sixth of the distance the signal travels during its rise time. Signals on outer-layer FR-4 travel at roughly 16 to 17 cm/ns (about 6.5 in/ns), so a 1 ns edge needs attention from about 2.5 to 3 cm (1 to 1.2 in).

In practice the interface spec answers the question before any calculation does. If your board has any of the following, design for controlled impedance from the start.

Interface	Target impedance	Notes
RF (antenna, coax connector, module RF pin)	50 Ω single-ended	Wi-Fi, BLE, LTE, GNSS and so on
USB 2.0 High Speed (480 Mbps)	90 Ω differential	spec allows ±15%
USB 3.x	85 to 90 Ω differential	check the generation's design guide
Ethernet (100BASE-TX, 1000BASE-T, PHY to magnetics)	100 Ω differential	per the PHY design guide
HDMI, LVDS, MIPI	100 Ω differential	per the chip vendor's layout guide
PCIe	85 Ω differential (check per generation)	per the board design guide
DDR memory	40 to 60 Ω single-ended (per design guide)	length matching is the bigger job

What sets impedance, and why stack-up comes first

The impedance of an outer-layer microstrip depends on trace width (W), dielectric height to the reference plane (H), dielectric constant (Dk, εr), copper thickness (T) and solder mask. The only one you change in CAD is width; everything else is fixed by the stack-up. So a width calculated before the stack-up is chosen means nothing. The same 50 Ω on a 1.6 mm (0.062 in) two-layer board (H ≈ 1.5 mm, 60 mil) needs a trace about 2.8 mm (110 mil) wide, wider than the connector pad, while on the outer layer of a four-layer board (H ≈ 0.2 mm, 8 mil) it shrinks to about 0.35 mm (14 mil). That is why boards with high-speed interfaces go to four layers or more.

For a first estimate, people use the microstrip approximation published in IPC-2141: Z₀ ≈ 87 / √(εr + 1.41) × ln(5.98H / (0.8W + T)). With H = 0.2 mm (8 mil), εr = 4.3 and 1 oz copper, it gives a 50 Ω width of about 0.34 mm (13 mil). A more accurate closed-form model (Hammerstad-Jensen) gives about 0.36 mm (14 mil). Approximations disagree by several percent, and solder mask lowers microstrip impedance by a few ohms. So design-stage numbers are starting values; the final width is the one the fab calculates from its actual material data.

⚠ Don't finalize differential impedance with an approximation

In a differential pair, the spacing (S) between the two traces changes impedance as much as width does. The approximation says W 0.2 mm / S 0.15 mm (8/6 mil) on 0.2 mm dielectric is about 100 Ω, but that only points you in the right direction. Always finalize differential impedance with a field-solver-based calculator or the fab's own calculation.

Order of operations: agree on the stack-up first

Get the fab's standard stack-up table. Most fabs publish standard stack-ups by layer count and thickness (core and prepreg thickness, material, Dk). For low-volume prototypes, picking one of these is the cheapest and fastest route.
Assign reference planes. Arrange layers so the layer directly below (or above) every impedance trace is an unbroken ground plane. On four layers the default is L1 signal / L2 GND / L3 power / L4 signal; if L4 traces reference the L3 power plane, say so in the notes.
Calculate width and spacing for that stack-up. Use the fab's impedance calculator or a field solver, and put the results into your CAD rules (net classes and differential-pair rules).
Have the fab review the design. Send impedance requirements with the Gerbers; the fab recalculates with real materials and proposes width adjustments. Decide in advance, in the notes, whether adjustment is allowed and by how much.
Specify measurement and reporting. If you want a coupon TDR report, request it with the order.

What ±10% means, and coupons and TDR

On standard processes, ±10% impedance tolerance is typical; ±5 to 7% is a premium spec that costs more and needs tighter process control. 50 Ω ±10% means 45 to 55 Ω. The tolerance comes from post-etch width variation (tens of microns, around a mil), prepreg thickness variation, Dk variation and frequency dependence, and plating thickness variation. Most interface specs accept ±10% comfortably (USB 2.0 High Speed allows ±15%, for example).

The fab doesn't measure the traces on your finished board. It builds test coupons on the panel rail with the same layer, width and reference plane as your design traces and measures them with a TDR (time-domain reflectometer). The method is defined in IPC-TM-650 2.5.5.7. Because coupons come from the same panel and process, they represent your traces, but they are not your traces. If the reference plane is broken under a board trace, or copper sits right next to it, that trace can be off no matter how well the coupon measured. Think of it this way: the coupon proves the fab kept its promise; your design rules make sure the board matches the coupon's conditions.

Worked example: USB and RF on a four-layer board

Take a four-layer, 1.6 mm board with an ESP32 chip placed directly (not a module), USB 2.0 and a 2.4 GHz antenna feed. If the fab's standard stack-up has about 0.2 mm (8 mil) outer prepreg with Dk around 4.4, the starting values are: (1) RF 50 Ω on L1 referenced to L2, about 0.35 mm (14 mil) wide. Keep it short and straight to the matching network, and either keep the side ground pour well away (about three times the dielectric height or more) or calculate it as grounded coplanar waveguide (CPWG) from the start. (2) USB 90 Ω differential on L1 referenced to L2, width and spacing from the fab's calculator, registered as a differential-pair rule. (3) A table in the notes with both entries, stating that the fab may adjust width within ±10%. When the fab comes back with 'suggest adjusting 50 Ω width from 0.35 to 0.33 mm', that is the process working as intended.

What to put in the fab drawing and order notes

Item	Example	Why
Stack-up	fab's standard stack-up ID, or a per-layer thickness and material table	the premise of every impedance number
Impedance table	L1 / ref L2 / single-ended 50 Ω ±10% / W 0.35 mm (14 mil)	states exactly what to hit
Differential pairs	L1 / ref L2 / 90 Ω diff ±10% / W and S values / nets USB_DP, USB_DN	spacing is a key variable
Identification	impedance traces drawn at a unique width (e.g. 0.201 mm)	how CAM finds the traces
Adjustment allowed	width may be adjusted ±10% to meet impedance; stack-up thickness changes need prior approval	sets the negotiation range up front
Measurement and report	coupon TDR report requested	evidence of compliance
Solder mask	mask over impedance traces (included in calculation)	a condition worth a few ohms

The unique-width trick

If you draw impedance traces at a common width like 0.2 mm (8 mil), CAM can't tell them apart from ordinary signals of the same width and doesn't know which lines to compensate. Use a width that appears nowhere else on the board, such as 0.201 mm, and the fab can select exactly those traces. Then note the mapping, e.g. '0.201 mm traces = 90 Ω differential'.

Common mistakes

Choosing widths before the stack-up. Order from a different fab or stack-up and the whole calculation is void.
Crossing a break in the reference plane. The moment a trace crosses a split or slot, impedance and return path both break. The coupon passes and the board fails.
Pouring ground too close. A ground pour hugging a microstrip pulls its impedance down unintentionally. Keep clearance or calculate as coplanar from the start.
Leaving solder mask out of the calculation. Mask is worth a few ohms; confirm whether the fab's calculation includes it.
Specifying impedance on every net. Only flag the nets that need it, so the fab can control them and cost stays down.
Demanding ±5% on a budget process. It may be possible but costs much more, and ±10% suits most interfaces.
Not checking whether inner copper is 0.5 oz or 1 oz. It directly affects stripline impedance.
Forgetting vias and connectors. A 50 Ω trace can still see a large discontinuity at a connector pad or a layer-change via. The higher the frequency, the fewer vias, and place a ground via next to each signal via.

Practical checklist

Have you listed the nets that need impedance control, with target and tolerance?
Did you pick a standard stack-up and get per-layer thickness, Dk and copper weight?
Does every impedance trace have an unbroken reference plane?
Did you calculate width and spacing for that stack-up and enter them as CAD rules?
Are impedance traces drawn at a unique width?
Did you check clearance to side ground pours, or calculate as coplanar?
Do the notes include stack-up, impedance table, allowed adjustment and a TDR report request?
Did you review and approve the fab's width-adjustment proposal?

FAQ

Can I get 50 Ω on a two-layer board?

Yes, but a 50 Ω microstrip on a 1.6 mm two-layer board is about 2.8 mm (110 mil) wide. In practice you use a thinner board such as 0.8 mm (0.031 in), or grounded coplanar waveguide (CPWG) with ground on both sides to narrow the trace. See our layer-count article for choosing layers.

What happens if I don't select impedance control?

The fab builds to your Gerbers and neither measures nor guarantees impedance. If you designed to its standard stack-up you will usually land close, but an out-of-tolerance result isn't a defect.

What do I look for in a TDR report?

Whether each coupon's measured impedance is within target ± tolerance. Reports typically list coupon number, layer, target, measured value and pass/fail.

Is length matching part of impedance control?

No. Length matching is the designer's job in CAD; the fab isn't involved. Intra-pair skew and pair-to-pair skew follow the limits in each interface's design guide.