KEMI Docs · Design Practice
From Schematic to PCB — Netlists, Footprints, Pin Count
Last updated: 2026-08-30
A schematic is a logical document — what connects to what. The PCB layout realises it in physical space. The bridge between them is the netlist and the footprints, and understanding that bridge also explains why layout work is quoted by pin count.
1
The netlist — the schematic minus the drawing
A netlist is pure connectivity: 'net VCC touches U1 pin 8, C1 pin 1, R3 pin 2'. The PCB tool turns it into the ratsnest of required connections, then checks the finished routing back against it. Fix the schematic, re-export, apply as an ECO — never rewire connections directly on the board, or schematic and board silently diverge.
2
Footprints — where 80% of accidents happen
- Wrong package variant — the same IC ships as SOIC, TSSOP and QFN. Order one, footprint another, assemble nothing.
- Pin-mapping errors — symbol pin numbers mismatched to pad numbers produce a board that verifies clean and is wired wrong. Transistors (EBC/BCE) and connectors are the classic victims.
- Connector orientation — pin 1 flipped versus the mating cable. Imagine the physical mating.
- Home-made footprints with dimension errors — compare 1:1 against the datasheet land pattern.
Verify new footprints against reality
Print the board 1:1 and place the physical part, or at minimum compare numbers against the datasheet's recommended land pattern. KEMI registers new footprints into its unified library only after datasheet dimension checks.
3
Pin count — the measure of layout effort
Layout effort scales with pins, not parts: every pin is a connection to route. A hundred 2-pin resistors (200 pins) and two 100-pin MCUs (200 pins) differ 50x in part count but are similar routing jobs. That is why layout services industry-wide — KEMI included — quote by pin count, and why counting pins from the schematic is the fastest way to gauge a job before committing.
4
What to prepare for a layout request
- The schematic — CAD source or netlist, not only a PDF, so ECOs and verification are possible.
- Board outline, size limits, and fixed-position parts (connectors, switches, LEDs, mounting holes).
- Special rules — high-current paths, impedance-controlled nets, analog partitioning.
- Target layer count and fab process limits, if already decided.
FAQ
How do I count pins?
Your CAD's BOM/statistics can, or upload a KiCad/Eagle schematic or netlist to KEMI's Pin Counter for instant per-component counts. Watch multi-part symbols for double counting.
Can I patch the board without the schematic?
As an emergency, yes — then back-annotate immediately. Projects where board and schematic diverge always blow up at the next revision.
Can layout be quoted from a PDF schematic?
Yes, but redrawing the circuit into CAD gets added to the work. A CAD source or netlist removes that cost.
See also
This article summarises the working rules KEMI uses in real design and fabrication work. For production, part datasheets and fab specifications take precedence.